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LG Semicon Co.,Ltd.
REVISION HISTORY
/ Revision 1.0: July 1998 - Add PC100,7K(2-2-2) Specifications. - Update Icc Specifications. - Change Input Test Condition from 2.8/0.0V to 2.4/0.4V. - Added post SPD Information separately(7K/7J/10K) for Modules. - Add Minimum Capacitance Value for Component.
Rev. 1.0
LG Semicon Co.,Ltd.
Description
The GM72V66841CT/CLT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841CT/CLT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 125 Mhz.
GM72V66841CT/CLT
2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM
Pin Configuration
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Features
* PC100,PC66 Compatible 7K(2-2-2), 7J(3-2-2), 10K(PC66) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 100/125 MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh/ Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit *JEDEC Standard 54Pin 400mil TSOP II Package
JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW)
VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Pin Name
CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ VCC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask VCC for DQ VSS for DQ Power for internal circuit Ground for internal circuit No Connection
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GM72V66841CT/CLT
Block Diagram
A0 to A13
A0 to A8
A0 to A13
Column address counter
Column address buffer
Row address counter
Refresh counter
Row decoder
Row decoder
Row decoder
Row decoder
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Column decoder
Column decoder
Column decoder
Bank 0 4096 row x 512 column x 8 bit
Bank 1 4096 row x 512 column x 8 bit
Bank 2 4096 row x 512 column x 8 bit
Column decoder
Memory array
Memory array
Memory array
Sense amplifier & I/O bus
Memory array Bank 3 4096 row x 512 column x 8 bit
Input buffer
Output buffer
Control logic & timing generator
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DQM
RAS
CAS
CS
CLK
CKE
WE
DQ0 to DQ7
LG Semicon
GM72V66841CT/CLT
Pin Description
Pin Name CLK (input pin) CKE (input pin) DESCRIPTION CLK is the master Clock input to this pin. The other input signals are referred at CLK rising edge. This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for Power-down and Clock suspend modes. When CS is Low, the command input cycle becomes valid. When CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address(AY0 to AY8; GM72V66841CT/CLT) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the Precharge mode. When A10 = High at the Precharge command cycle, all banks are Precharged. But when A10 = Low at the Precharge command cycle, only the bank that is selected by A12/A13 (BS) is Precharged.
CS (input pin)
RAS, CAS, and WE (input pins)
A0 ~ A11 (input pins)
A12/A13 (input pin)
A12/A13 are bank select signal (BS). The memory array of the GM72V66841CT/CLT is divided into bank 0, bank 1, bank2 and bank 3. GM72V66841CT/CLT contain 4096-row x 512-column x 8-bits. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected.
DQM, DQMU/DQML (input pins)
DQM, DQMU/DQML controls input/output buffers. * Read operation: If DQM, DQMU/DQML is High, The output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. * Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written.
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GM72V66841CT/CLT
Pin Description(Continued)
Pin Name DQ0 ~ DQ7 (I/O pins) VCC and VCCQ (Power supply pins) VSS and VSSQ (Power supply pins) NC DESCRIPTION Data is input and output from these pins. These pins are the same as those of a conventional DRAM. 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) No Connection pins.
Command Operation Command Truth Table
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Function Ignore command No Operation Burst stop in full page Column address and read command Read with auto-Precharge Column address and write command Symbol DESL NOP BST READ READ A WRIT CKE n n-1 H H H H H H H H H H H H X X X X X X X X X X V X CS H L L L L L L L L L L L RAS X H H H H H H L L L L L CAS X H H L L L L H H H L L WE X H L H H L L H L L H L A12~ A13 X X X V V V V V V X X V A10 X X X L H L H V L H X V A0~ A11 X X X V V V V V X X X V
Write with auto-Precharge WRIT A Row address strobe and bank active Precharge select bank Precharge all banks Refresh Mode register set ACTV PRE PALL REF/SELF MRS
* Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input
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Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignores command input at the Clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full page [BST] : This command stops a full-page burst operation (burst length = full-page(512;GM72V66841CT/CLT) and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for full-page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13). After the read operation, the output buffer becomes High-Z. Read with auto-Precharge [READ A]: This command automatically performs a Precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY8;GM72V66841CT/CLT) and the bank select address (A12/A13).
GM72V66841CT/CLT
Write with auto-Precharge [WRIT A]: This command automatically performs a Precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13(BS) and determines the row address (AX0 to AX11). If A12 is Low and if A13 is Low, bank 0 is activated. If A12 is High and A13 is Low, bank 1 is activated. If A12 is Low and A13 is High, bank 2 is activated. If A12 is High and A13 is High, bank 3 is activated. Precharge selected bank [PRE]: This command starts Precharge operation for the bank selected by A12/A13. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. Precharge all banks [PALL]: This command starts a Precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After Power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
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GM72V66841CT/CLT
DQM Truth Table
Function Write enable/output enable Write inhibit/output disable * Notes : H: VIH, L: VIL, X: VIH or VIL. Write : lDID is needed. Read : lDOD is needed. The GM72V66841CT/CLT can mask input/output data by means of DQM. During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQM. For details, refer to the DQM control section of the GM72V66841CT/CLT operating instructions. Symbol ENB MASK CKE n-1 H H n X X DQM L H
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GM72V66841CT/CLT
CKE Truth Table
Current State Active Any Clock Suspend CKE Function Clock suspend mode entry Clock suspend Clock suspend mode exit Auto-refresh command Self-refresh entry Power down entry Self refresh exit Power down Exit (SELFX) (REF) n -1 H L L n L L H CS H X X RAS X X X CAS X X X WE X X X Address X X X
Idle
H
H
L
L
L
H
X
Idle
(SELF)
H H H L L L L
L L L H H H H
L L H L H L H
L H X H X H X
L H X H X H X
H H X H X H X
X X X X X X X
Idle
Self refresh
Power down
* Notes : H: VIH, L: VIL, X: VIH or VIL.
Clock suspend mode entry: The synchronous DRAM enters Clock suspend mode from active mode by setting CKE to Low. The Clock suspend mode changes depending on the current status (1 Clock before) as shown below. ACTIVE Clock suspend: This suspend mode ignores inputs after the next Clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output).
WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During Clock suspend mode, keep the CKE to Low. Clock suspend mode exit : The synchronous DRAM exits from Clock suspend mode by setting CKE to High during the Clock suspend state. IDLE: In this state, all banks are not selected, and completed Precharge operation.
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Auto-refresh command[REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4,096 times are required to refresh the entire memory. Before executing the autorefresh command, all the banks must be in the IDLE state. In addition, since the Precharge for all banks is automatically performed after autorefresh, no Precharge command is required after auto-refresh. Self-refresh entry[SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary.
GM72V66841CT/CLT
Self-refresh exit[SELFX]: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters Power down mode. In Power down mode, Power consumption is suppressed by cutting off the initial input circuit. Power down exit: When this command is executed at the Power down mode, the synchronous DRAM can exit from Power down mode. After exiting from Power down mode, the synchronous DRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state Precharge CS H L L L L L L RAS X H H H H L L CAS X H H L L H H WE X H L H L H L X X X Address Command DESL NOP BST Operation Enter IDLE after Enter IDLE after NOP
tRP tRP
BA, CA, A10 READ/READ A ILLEGAL BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 ACTV PRE, PALL ILLEGAL ILLEGAL NOP
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GM72V66841CT/CLT
Function Truth Table (Continued)
Current state Precharge CS L L Idle H L L L L L L L L Row active H L L L L L RAS L L X H H H H L L L L X H H H H L CAS L L X H H L L H H L L X H H L L H WE H L X H L H L H L H L X H L H L H X MODE X X X Address Command REF, SELF MRS DESL NOP BST Operation ILLEGAL ILLEGAL NOP NOP NOP
BA, CA, A10 READ/READ A ILLEGAL BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 X MODE X X X ACTV PRE, PALL REF, SELF MRS DESL NOP BST ILLEGAL Bank and row active NOP Refresh Mode register set NOP NOP NOP
BA, CA, A10 READ/READ A Begin read BA, CA, A10 WRIT/WRIT A BA, RA ACTV Begin write Other bank active *3 ILLEGAL on same bank Precharge ILLEGAL ILLEGAL
L L L
L L L
H L L
L H L
BA, A10 X MODE
PRE, PALL REF, SELF MRS
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GM72V66841CT/CLT
Function Truth Table (Continued)
Current state Read CS H L L L RAS X H H H CAS X H H L WE X H L H X X X Address Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop to full page
BA, CA, A10 READ/READ A Continue burst read to CAS latency and New read BA, CA, A10 WRIT/WRIT A BA, RA ACTV Term burst read/start write Other bank active *3 ILLEGAL on same bank Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and Precharge Continue burst to end and Precharge ILLEGAL
L L
H L
L H
L H
L
L
H
L
BA, A10
PRE, PALL
L L Read with autoPrecharge H
L L X
L L X
H L X
X MODE X
REF, SELF MRS DESL
L
H
H
H
X
NOP
L L L L
H H H L
H L L H
L H L H
X
BST
BA, CA, A10 READ/READ A ILLEGAL BA, CA, A10 WRIT/WRIT A BA, RA ACTV ILLEGAL Other bank active *3 ILLEGAL on same bank ILLEGAL ILLEGAL ILLEGAL
L L L
L L L
H L L
L H L
BA, A10 X MODE
PRE, PALL REF, SELF MRS
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GM72V66841CT/CLT
Function Truth Table (Continued)
Current state Write CS H L L L L L RAS X H H H H L CAS X H H L L H WE X H L H L H X X X Address Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop on full page
BA, CA, A10 READ/READ A Term burst and New read BA, CA, A10 WRIT/WRIT A BA, RA ACTV Term burst and New write Other bank active *3 ILLEGAL on same bank Term burst write and *2 Precharge ILLEGAL ILLEGAL Continue burst to end and Precharge Continue burst to end and Precharge ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
L L Write with autoPrecharge H
L L X
L L X
H L X
X MODE X
REF, SELF MRS DESL
L
H
H
H
X
NOP
L L L L
H H H L
H L L H
L H L H
X
BST
BA, CA, A10 READ/READ A ILLEGAL BA, CA, A10 WRIT/WRIT A BA, RA ACTV ILLEGAL Other bank active *3 ILLEGAL on same bank ILLEGAL ILLEGAL ILLEGAL
L L L
L L L
H L L
L H L
BA, A10 X MODE
PRE, PALL REF, SELF MRS
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GM72V66841CT/CLT
Function Truth Table (Continued)
Current state Refresh (auto-refresh) CS H L L L L L L L L RAS X H H H H L L L L CAS X H H L L H H L L WE X H L H L H L H L X X X Address Command DESL NOP BST Operation Enter IDLE after Enter IDLE after Enter IDLE after
tRC tRC tRC
BA, CA, A10 READ/READ A ILLEGAL BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 X MODE ACTV PRE, PALL REF, SELF MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
* Notes : 1. H: VIH, L: VIL, X: VIH or VIL. The other combinations are inhibit. 2. An interval of tRWL is required between the final valid data input and the Precharge command. 3. If tRRD is not satisfied, this operation is illegal. 4. BA:Bank Address, RA:Row Address, CA:Column Address From [Precharge] To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of Precharge From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM to Precharge mode. (However, an interval of tRAS is required.)
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From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters Precharge mode. From [READ with AUTO-Precharge] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [WRITE]
GM72V66841CT/CLT
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters Precharge mode.
From [WRITE with AUTO-Precharge] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an autorefresh cycle (after tRC), the synchronous DRAM automatically enters the Idle state.
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GM72V66841CT/CLT
64M SDRAM Function State Diagram
SELFREFRESH
E SR
NT
RY
MODE REGISTER SET
MRS
IT EX SR
IDLE
REFRESH
CKE =L
AUTOREFRESH IDLE Power DOWN
*1
ACTIVE Clock SUSPEND
CK E= H
CKE =H
ACTIVE
CK E= L
BST (on full page)
W RI TE
ROW ACTIVE
RE AD
AP
AP TH WI AD RE
BST (on full page)
Write CKE=L
WI
TH
Read CKE=L
WR
ITE
READ
RE A WI D TH AP
PRECHARGE
WRITE SUSPEND
WRITE
CKE=H WRITE WITH AP CKE=L
READ
WRITE
READ SUSPEND
ITE WR H AP IT W
PR EC HA RG E
CKE=H READ WITH AP
WRITEA SUSPEND
CKE=L
E RG HA EC PR
WRITEA
CKE=H
READA
CKE=H
READA SUSPEND
Power APPLIED
Power ON
PRECHARGE
Precharge
Automatic Transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, Precharge is performed automatically and enter the IDLE state.
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GM72V66841CT/CLT
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified . When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
A13 A12 A11 A10 A9 OPCODE
A8
A7 0
A6
A5 LMODE
A4
A3 BT
A2
A1 BL
A0
A6 A5 A4 CAS Latency 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X R R 2 3 R
A3 Burst Type A2 A1 A0 0 Sequential 1 Interleave 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Burst Length BT=0 BT=1 1 2 4 8 R R R F.P. 1 2 4 8 R R R R
A13 A12 A11 A10 A9 0 X X X 0 X X X 0 X X X 0 X X X 0 0 1 1
A8 0 1 0 1
Write mode Burst read and BURST WRITE R Burst read and SINGLE WRITE R
1 1
F.P. = Full Page (512:GM72V66841CT/CLT) R is Reserved (inhibit) X: 0 or 1
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GM72V66841CT/CLT
Burst Sequence
Burst Length Starting Column Address A2 A1 A0 V 2 V V V 4 V V 0 0 0 0 8 1 1 1 1 V V 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Addressing(decimal) Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Interleave 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
* Notes : V : Valid Address
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GM72V66841CT/CLT
Operation of GM72V661641CT/CLT, GM72V66841CT/CLT, GM72V66441CT/CLT Series
Read / Write Operation Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. GM72V66841CT/CLT can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full page(512;GM72V66841CT/CLT). The start address for a burst read is specified by the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (512;GM72V66841CT/CLT) data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register.
CAS Latency
CLK
tRCD
Command
Address ACTV READ
Row
Column
CL = 2 Dout CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3 CL : CAS Latency Burst Length = 4
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Burst Length
CLK
GM72V66841CT/CLT
tRCD
Command Address
Active Read Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
out 0 out 1 out 2 out 3
Dout
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0-1 out 0
out 1
BL = Full Page BL = Burst Length CAS Latency = 2
Write Operation Burst write or single write mode is selected by the OPCODE(A13, A12,A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE(A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8 and full page, like burst read operations. The write start address is specified by the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) at the write command set cycle.
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.)
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LG Semicon
Burst Write
CLK
GM72V66841CT/CLT
tRCD
Command Address
ACTV WRIT Row
Column
in 0
BL = 1
in 0 in 1
BL = 2
in 0 in 1 in 2 in 3
Din
BL = 4
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7
BL = 8
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 in 9 in 10 in 11 in 0-1 in 0 in 1
BL = Full Page CAS Latency = 2, 3
Single Write
CLK
tRCD
Command
ACTV WRIT
Address
Row
Column
Din
in 0
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Auto Precharge Read with auto-Precharge: In this operation, since Precharge is automatically performed after completing a read operation, a Precharge command need not be executed after each read operation.
GM72V66841CT/CLT
The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command.
CAS Latency 3 2
Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output
Burst Read with Auto-Precharge
CLK CL=2 Command
READ
ACTV
Dout
out 0
out 1
out 2
out 3
lAPR
CL=3 Command READ ACTV
Dout
out 0
out 1
out 2
out 3
lAPR
Note : Internal auto-Precharge starts at the timing indicated by " " At CLK=50MHz (lAPR changes depending on the operating frequency.)
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LG Semicon
Write with auto-Precharge: In this operation, since Precharge is automatically performed after completing a burst write or single write operation, a Precharge command need not be executed after each write operation.
GM72V66841CT/CLT
The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of the next command.
Burst Write (Burst Length = 4)
CLK Command WRIT in 0 in 1 in 2 in 3 ACTV
DQ(input)
lAPW
Single Write
CLK Command DQ(input) WRIT in ACTV
lAPW
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LG Semicon
Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read.
GM72V66841CT/CLT
The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4, and 8.
CAS Latency 2 3
BST to valid data 1 2
BST to high impedance 2 3
CAS Latency=2, Burst Length = full page
CLK Command DQ(output) out out out out BST out out
lBSH = 2 cycle lBSR = 1 cycle
CAS Latency = 3, Burst Length = full page
CLK Command DQ(output) out out out out BST out out out
lBSH = 3 cycle lBSR = 2 cycle
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LG Semicon
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command, and in subsequent cycles.
GM72V66841CT/CLT
In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4, and 8. And an interval of tRWL is required between the last data-in and the next Precharge command.
Burst Length = full page
CLK Command DQ(output) in in BST
PRE/PALL
tRWL
lBSW = 0 cycle
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LG Semicon
Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. READ to READ Command Interval (Same Row Address in Same Bank)
GM72V66841CT/CLT
Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK
Command Address (A0-A11) BS(A12/A13)
ACTV
READ
READ
Row
Column A Column B
Dout
Bank0 Active Column=A Column=B Read Read
out A0
out B0
out B1
out B2
out B3
Column=A Column=B
Dout
Dout
CAS Latency =3 Burst Length = 4 Bank0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a Precharge command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
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LG Semicon
READ to READ Command Interval (different bank)
GM72V66841CT/CLT
CLK
Command Address (A0-A11)
ACTV
ACTV
READ
READ
Row 0
Row 1
Column A Column B
BS(A12/A13)
Dout
Bank0 Active Bank3 Bank0 Active Read Bank3 Read
out A0
out B0
out B1
out B2
out B3
Bank0 Dout
Bank3 Dout
CAS Latency = 3 Burst Length = 4
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LG Semicon
Command Intervals Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. WRITE to WRITE Command Interval (same ROW address in same bank)
CLK
GM72V66841CT/CLT
In the case of burst writes, the second write command has priority.
Command Address (A0-A11) BS(A12/A13)
ACTV
WRIT
WRIT
Row
Column A
Column B
Din
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Column=A Column=B Write Write
Burst Write Mode Burst Length = 4 Bank0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two write commands with a Precharge command and a bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. In the case of burst write, the second write command has priority.
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LG Semicon
WRITE to WRITE Command Interval (different bank)
CLK
GM72V66841CT/CLT
Command Address (A0-A11)
ACTV
ACTV
WRIT
WRIT
Row 0
Row 1
Column A Column B
BS(A12/A13)
Din
in A0
in B0
in B1
in B2
in B3
Bank0 Active
Bank3 Bank0 Active Write
Bank3 Write
Burst Write Mode Burst Length = 4
Read command to Write command interval: 1. Same bank, same Row address: When the write command is executed at the same ROW address of the same bank as the preceding READ to WRITE Command Interval (1)
CLK READ WRIT
read command, the write command can be performed after an interval of no less than 1 cycle. However, DQM, DQMU/DQML must be set High-Z so that the output buffer becomes High-Z before data input.
Command
DQM, DQMU /DQML
CL=2
CL=3
Din
in B0 High-Z
in B1
in B2
in B3
Dout
Burst Length = 4 Burst Write
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LG Semicon
READ to WRITE Command Interval (2)
CLK
GM72V66841CT/CLT
Command DQM, DQMU /DQML
READ
WRIT
2 Clock High-Z High-Z
CL=2 Dout CL=3
Din
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a Precharge command or a bank-active command.
3. Different bank: When the bank changes, the write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input.
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LG Semicon
Write Command to Read Command Interval: 1. Same bank, same Row address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the write command can be performed after an interval of no less than 1 cycle. WRITE to READ Command Interval (1)
CLK
GM72V66841CT/CLT
However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed.
Command
WRIT
READ
DQM, DQMU/DQML
Din
in A0
Dout
CAS Latency Column=A Write Column=B Read
out B0
out B1
out B2
out B3
Column=B Dout
Burst Write Mode CAS Latency=2 Burst Length = 4 Bank0
WRITE to READ Command Interval (2)
CLK
Command
WRIT
READ
DQM, DQMU/DQML
Din
in A0
in A1
Dout
CAS Latency Column=A Write Column=B Read
out B0
out B1
out B2
out B3
Column=B Dout
Burst Write Mode CAS Latency=2 Burst Length = 4 Bank0
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LG Semicon
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a Precharge command and a bank-active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed(as in the case of the same bank and the same address).
GM72V66841CT/CLT
Read command to Precharge interval (same bank): When the Precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the Precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to Precharge command execution.
READ to Precharge Command Interval (same bank) : To output all data CAS Latency = 2, Burst Length = 4
CLK
Command
READ
PRE/PALL
Dout
out A0
out A1
out A2
out A3
CL=2
lEP = -1 Cycle
CAS Latency = 3, Burst Length = 4
CLK
Command
READ
PRE/PALL
Dout CL=3
out A0
out A1
out A2
out A3
lEP = -2 Cycle
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LG Semicon
GM72V66841CT/CLT
READ to Precharge Command Interval (same bank) : To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8
CLK
Command
READ
PRE/PALL
High - Z Dout out A0
lHZP=2
CAS Latency = 3, Burst Length = 1, 2, 4, 8
CLK
Command
READ
PRE/PALL
High - Z Dout out A0
IHZP=3
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LG Semicon
Write Command to Precharge Command Interval (same bank): When the Precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle.
GM72V66841CT/CLT
However, if the burst write operation is unfinished, the input data must be masked by means of DQM, DQMU/DQML for assurance of the cycle defined by tRWL.
Burst Length = 4 ( To stop write operation)
CLK
Command
WRIT
PRE/PALL
DQM, DQMU/DQML
Din
tRWL
CLK
Command
DQM, DQMU/DQML
WRIT
PRE/PALL
Din
in A0
in A1
tRWL
Burst Length = 4 (To write all data)
CLK
Command
WRIT
PRE/PALL
DQM, DQMU/DQML
Din
in A0
in A1
in A2
in A3
tRWL
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LG Semicon
Bank Active Command Interval 1. Same bank: The interval between the two bank-active commands must be no less than tRC.
GM72V66841CT/CLT
2. In the case of different bank-active commands: The interval between the bankactive commands must be no less than tRRD.
Bank Active to Bank Active Command Interval for Same Bank
CLK
ACTV ACTV
Command Address (A0-A11) BS(A12/A13)
ROW
ROW
tRC
Bank 0 Active Bank 0 Active
Bank Active to Bank Active for different bank
CLK
Command Address (A0-A11)
ACTV
ACTV
ROW:0
ROW:1
BS(A12/A13)
tRRD
Bank 0 Active Bank 3 Active
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LG Semicon
Mode Register Set to Bank-Active Command Interval : The interval between setting the mode register and executing a bank-active command must be no less than tRSA.
GM72V66841CT/CLT
CLK
Command
MRS
ACTV
Address (A0-A13)
CODE
BS & ROW
tRSA
Mode Register Set Bank Active
DQM Control (GM72V661641CT/CLT) The DQMU and DQML mask the upper and lower bytes of DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2. Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0.
DQM Control (GM72V66841CT/CLT,GM72V66441CT) The DQM mask DQ data. The timing of DQM is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2. Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0.
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LG Semicon
Reading
CLK DQM, DQMU/DQML DQ (input)
GM72V66841CT/CLT
out 0
out 1
High-Z
out 3
lDOD = 2 Latency
Writing
CLK DQM, DQMU/DQML DQ (input)
in 0
in 1
in 3
lDID
= 0 Latency
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Refresh Auto refresh: All the banks must be Precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4,096 cycles/64ms. (4,096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-Z after auto-refresh start. In addition, since a Precharge has been completed by an internal operation after the auto-refresh, an additional Precharge operation by the Precharge command is not required. Self refresh: After executing a self-refresh command, the selfrefresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a selfrefresh exit command. If you use distributed auto-refresh mode with 15.6us interval in normal read/write cycle, auto-refresh should be executed within 15.6 us immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6us interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power down mode: The synchronous DRAM enters Power down mode when CKE goes Low in the IDLE state. In Power down mode, Power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the Power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed.
GM72V66841CT/CLT
Clock suspend (Active Power down) mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters Clock suspend mode. During Clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates Clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". Power-up sequence: During Power-up sequence, the DQM and the CKE must be set to High. When 200A has past after Power on, all banks must be Precharged using the Precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register.
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LG Semicon
GM72V66841CT/CLT
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Notes : 1. Respect to VSS Symbol VT VCC IOUT PT Topr Tstg Value -0.5 to Vcc+0.5 (<= 4.6 (max)) -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1
Recommended DC Operating Conditions (Ta = 0 to + 70C)
Parameter Supply voltage VSS, VSSQ Input high voltage Input low voltage Notes : 1. All voltage referred to VSS. 2. VIH (max) = 4.6V for pulse width <= 5ns 3. VIL (min) = -1.5V for pulse width <= 5ns VIH VIL 0 2.0 -0.3 0 Vcc + 0.3 0.8 V V V 1, 2 1,3 Symbol VCC, VCCQ Min 3.0 Max 3.6 Unit V Note 1
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LG Semicon
GM72V66841CT/CLT
DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V)
Parameter Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) Active standby current in power down Symbol - 7K Max 80 2 2 ICC2PS 0.4 15 ICC2N 10 ICC2NS 5 6 ICC3P 5 5 4 30 ICC3N 25 20 10 120 120 110 1 Self refresh current ICC6 0.4 0.4 0.4 0.4 25 20 10 80 120 110 1 25 20 10 100 155 110 1 25 20 mA 10 80 120 90 1 mA mA mA mA 5 5 4 30 5 5 4 30 5 5 mA 4 30 mA 10 5 6 10 5 6 10 5 6 mA mA 0.4 15 0.4 15 0.4 15 mA - 7J Max 80 2 2 -8 Max 80 2 2 - 10K Max 70 2 2 mA Unit Test conditions Notes Burst length= 1 tRC = min CKE = VIL, tCK = 12 ns CKE=VIL, tCK= Infinity CKE,CS = VIH, tCK = 12ns CKE = VIH, tCK = Infinity CKE = VIL, tCK = 12 ns, DQ = High-Z CKE = VIL, tCK = Infinity
ICC1 ICC2P
mA mA
1, 2, 3 5 6 6,8 4 4,8 4 1,2,5 1,2,5,8 2,6 2,6,8
Active standby current in power down ICC3PS (input signal stable) Active standby current in non power down
CKE,CS = VIH, 1,2,4 tCK = 12 ns, 1,2,4,8 DQ = High-Z CKE = VIH, tCK = Infinity 2,9 2,8,9
Active standby current in non power down ICC3NS (input signal stable) Burst operating current ( CL= 2 ) ( CL= 3 ) ICC4 ICC4 ICC5
tCK = min
BL = 4
1,2,3
Refresh current
tRC = min
VIH >=VCC - 0.2 VIL <=.2V
3 7 7,8
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LG Semicon
- 7K, -7J, -8, -10K Min -1 -1.5 2.4 Max 1 1.5 0.4
GM72V66841CT/CLT
Parameter
Symbol
Unit Test conditions Notes
Input leakage current Output leakage current Output high voltage Output low voltage
ILI ILO VOH VOL
uA uA V V
0<=Vin <=VCC 0<=Vout <=VCC DQ = disable IOH = -2 mA IOL =2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. L-Version. 9. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V +/- 0.3 V)
Parameter Input capacitance (CLK) Input capacitance (Signals) Output capacitance (DQ) Symbol CI1 CI2 CO Min. 2.5 2.5 4.0 Max. 4 5 6.5 Unit pF pF pF Notes 1, 3, 4 1, 3, 4 1, 2, 3, 4
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM, DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. 4. Measured with 1.4 V bias and 200mV swing at the pin under measurement.
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LG Semicon
GM72V66841CT/CLT
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V)
Parameter System clock cycle time (CL=2) (CL=3) Symbol - 7K Min 10 10 3 3 3 2 2 1 2 1 2 2 1 2 Max 6 6 6 - 7J Min 15 10 3 3 3 2 2 1 2 1 2 2 1 2 Max 8 6 6 Min 12 8 3 3 3 2 2 1 2 1 2 2 1 2 -8 Max 8 6 6 - 10K Min 15 10 3 3 3 2 2 1 2 1 2 2 1 2 Max ns 9 ns 8 7 ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1, 2 ns ns 1 1 1 Unit Notes
CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3)
Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period
tCK tCK tCKH tCKL tAC tAC tOH tLZ tHZ tDS tDH tAS tAH tCES tCESP tCEH tCS
tCH tRC tRAS tRCD tRP
1 70 50 20 20
120000 -
1 70 50 20 20
120000 -
1 72 48 24 24
120000 -
1 90 60 30 30
120000 -
ns ns ns ns ns
1 1 1 1 1
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LG Semicon
GM72V66841CT/CLT
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) (Continued)
Parameter Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Symbol - 7K Min 10 20 1 Max 5 64 - 7J Min 10 20 1 Max 5 64 Min 10 16 1 -8 Max 5 64 - 10K Min 15 20 1 Max 5 64 Unit Notes ns ns ns ms 1 1
tRWL tRRD tT tREF
Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V. 2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination. 3. tLZ (min)defines the time at which the outputs achieves the low impedance state. 4. tHZ (max)defines the time at which the outputs achieves the high impedance state. 5. tCES define CKE setup time to CKE rising edge except Power down exit command.
Test Condition
- Input and output-timing reference levels: 1.4V - Input waveform and output load: See following figures I/O input 2.4V 0.4V 80% 20% CL OPEN
tT
tT
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LG Semicon
GM72V66841CT/CLT
Relationship Between Frequency and Minimum Latency
Parameter frequency(MHz) Symbol - 7K
100 10 100 10 2 7 5 2 1 2 1 3 9 3 1 -2 1 0 0 2 1 1 0 1
- 7J
66 15 2 6 4 2 1 2 1 3 6 2 3 1 -1 -2 1 0 0 2 1 1 0 1 125 8 3 9 6 3 2 2 1 5 9 3 1 -2 1 0 0 2 1 1 0 1
-8
83 12 2 6 4 2 1 2 1 3 6 2 3 1 -1 -2 1 0 0 2 1 1 0 1
- 10K
100 10 3 9 6 3 1 2 1 4 9 3 1 -2 1 0 0 2 1 1 0 1 66 15 2 6 4 2 1 2 1 3 6 2 3 1 -1 -2 1 0 0 2 1 1 0 1
Notes
tCK (ns)
Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command CS to command disable Power down exit to command input
lRCD lRC lRAS lRP lRWL lRRD lSREX lAPW lSEC lHZP lHZP lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lRSA lCDD lPEC
2 7 5 2 1 2 1 3 9 2 3 1 -1 -2 1 0 0 2 1 1 0 1
1 = [lRAS +lRP], 1 1 1 1 1
= [lRWL +lRP], 1 = [lRC]
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LG Semicon
GM72V66841CT/CLT
Relationship Between Frequency and Minimum Latency
Parameter frequency(MHz) Symbol - 7K
100 10 100 10 2 3 0
- 7J
66 15 1 2 2 3 0 125 8 2 3 0
-8
83 12 1 2 2 3 0
- 10K
100 10 2 3 0 66 15 1 2 2 3 0
Notes
tCK (ns)
Burst stop to output valid data hold Burst stop to output high impedance (CL=2) (CL=3) (CL=2) (CL=3)
Burst stop to write data ignore
lBSR lBSR lBSH lBSH lBSW
1 2 2 3 0
Notes : 1. lRCD to lRRD are recommended value.
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LG Semicon Timing Waveforms
GM72V66841CT/CLT
Read Cycle
tCK
tCKH tCKL CLK
tRC
CKE
VIH tRAS tCS tCH tRCD tCS tCH tCS tCH tRP tCS tCH
CS
tCS tCH
RAS
tCS tCH tCS tCH
tCS tCH tCS tCH
tCS tCH tCS tCH
tCS tCH
CAS
tCS tCH
WE
tCS tCH
tCS tCH
tCS tCH
tAS tAH
A12/A13
tAS tAH tAS tAH
tAS tAH
tAS tAH
tAS tAH
A10
tAS tAH
tAS tAH
tAS tAH
Address
tAS tAH tCS tCH
tAS tAH
.
DQM , DQMU/DQML
DQ(input)
tAC
DQ(output)
tAC
tAC
tAC
tHZ
tLZ
Bank0 Active Bank0 Read
tOH
tOH
tOH
Bank0 Precharge
tOH
CAS Latency = 2 Burst Length = 4 Bank0 Access = VIH or VIL
44
LG Semicon Write Cycle
tCK
tCKH tCKL CLK
GM72V66841CT/CLT
tRC
CKE
VIH tRAS tCS tCH tRCD tCS tCH tCS tCH tRP tCS tCH
CS
tCS tCH
RAS
tCS tCH tCS tCH
tCS tCH tCS tCH
tCS tCH tCS tCH
tCS tCH
CAS
tCS tCH
WE
tCS tCH
tCS tCH tAS tAH
tCS tCH
tAS tAH
A12/A13
tAS tAH tAS tAH
tAS tAH
tAS tAH
A10
tAS tAH
tAS tAH
tAS tAH
Address
tAS tAH
.
tAS tAH tCH
tCS
DQM , DQMU/DQML
tDS tDH tDS tDH tDS tDH tDS tDH
DQ(input)
tRWL
DQ(output)
Bank0 Active Bank0 Write Bank0 Precharge
CAS Latency = 2 Burst Length = 4 Bank0 Access = VIH or VIL
45
LG Semicon Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12
GM72V66841CT/CLT
13
14
15
16
17
18
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML valid code R:b C:b . C:b
VIH
DQ(output) DQ(input)
b High - Z
b+3
b
. b+1 b+2 b+3 ...
tRP
Precharge if needed
tRSA
Mode Bank3 Register Active Set
tRCD
Bank3 Read Output Mask
tRCD=3 CAS Latency=3 Burst Length=4 = VIH or VIL
46
LG Semicon Read Cycle/ Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13
GM72V66841CT/CLT
14 15 16 17 18 19 20
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a
VIH
C:a
R:b
C:b
. C:b
.. C:b
DQ(output) DQ(input)
Bank0 Active Bank0 Read Bank3 Active
a
a+1 a+2 a+3
b
b+1 b+2 b+3
. b
. b+1
.. .. .. .. b b+1 b+2 b+3
High-Z
Bank3 Bank0 Read Precharge Bank3 Read Bank3 Read Bank3 Precharge
Read Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a C:a R:b C:b . C:b .. C:b
VIH
DQ(output) DQ(input)
Bank0 Active a Bank0 Write a+1 a+2 a+3 Bank3 Active b Bank3 Write
High-Z
b+1 b+2 b+3 Bank0 Precharge . b . b+1 .. .. .. .. b b+1 b+2 b+3 Bank3 Precharge
Bank3 Write
Bank3 Write
Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL
47
LG Semicon Read / Single Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13
GM72V66841CT/CLT
14
15
16
17
18
19
20
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a C:a R:b . C:a C:a
VIH
DQ(input) DQ(output)
Bank0 Active Bank0 Read Bank3 Active a a+1 a+2 a+3
a a a+1 a+2 a+3
Bank0 Bank0 Write Read
Bank0 Bank3 Precharge Precharge
CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a
VIH
C:a
R:b
C:a
C:b C:c
DQ(input) DQ(output)
a a+1 a+3
a
b
c
Bank0 Active
Bank0 Read
Bank3 Active
Bank0 Write
Bank0 Bank0 Write Write
Bank0 Precharge
Read/Single Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL
48
LG Semicon Read / Burst Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13
GM72V66841CT/CLT
14
15
16
17
18
19
20
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a C:a R:b C:a ..
DQ(input) DQ(output)
Bank0 Active Bank0 Read Bank3 Active a a+1 a+2 Clock Suspend a+3
a
a+1 a+2 a+3
Bank0 Write
Bank0 Bank3 Precharge Precharge
CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML
VIH
R:a
C:a
R:b
C:a
..
DQ(input) DQ(output)
Bank0 Active Bank0 Read Bank3 Active a a+1 a+3
a
a+1 a+2 a+3
Bank0 Write
Bank0 Precharge
Read/Burst Write RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL
49
LG Semicon Full Page Read / Write Cycle
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a C:a R:b
GM72V66841CT/CLT
VIH
..
DQ(output) DQ(input)
Bank0 Active Bank0 Read Bank3 Active
a
a+1 a+2 a+3
a-2 a-1
a
.. .. .. a+1 a+2 a+3 a+4 a+5
High-Z
Burst Stop Bank3 Precharge
Read Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML R:a C:a R:b ..
VIH
DQ(input) DQ(output)
Bank0 Active
a
a+1 a+2 a+3 a+4 a+5 a+6
. a+1 a+2 a+3 a+4 a+5 .
. . Burst Stop
.. ..
.. ..
.. ..
.. ..
High-Z
Bank0 Write Bank3 Active
Bank1 Precharge
Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL
50
LG Semicon Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13
GM72V66841CT/CLT
14
15
16
17
18
19
20
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML
A10=h
VIH
R:a
C:a
DQ (input) DQ (output)
High-Z a a+1
tRP
Precharge if needed Auto Refresh
tRC
Auto Refresh
tRC
Bank0 Active Bank0 Read
Refresh Cycle and Read Cycle RAS-CAS Delay=2 CAS Latency=2 Burst Length=4 = VIH or VIL
51
LG Semicon Self Refresh Cycle
CLK CKE CS RAS CAS WE A12/A13 Address
DQM , DQMU/DQML
A10=h
GM72V66841CT/CLT
CKE Low
DQ
High-Z
tRP
Precharge Command if needed Self Refresh Entry Command
tRC
Self Refresh Exit Ignore Command of No Operation Next Self Refresh Clock Entry Command Enable
tRC
Next Auto Clock Refresh Enable
Self Refresh Cycle RAS-CAS Delay = 3 CAS Latency=3 Burst Length=4 = VIH or VIL
52
LG Semicon Clock Suspend (Active Power Down) Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13
GM72V66841CT/CLT
14 15 16 17 18 19 20
CLK CKE CS RAS CAS WE A12/A13(BS) Address
DQM , DQMU/DQML R:a C:a R:b C:b
DQ(output) DQ(input)
Bank0 Active Clock Active Suspend Start Bank0 Read
a
a+1
a+2 High-Z
a+3
b
b+1 b+2 b+3
Bank3 Bank0 Bank3 Read Suspend Read Precharge Active Start Read Suspend End Active Clock Suspend End
Earliest Bank3 Precharge
Read Cycle , RAS-CAS Delay=2 CAS Latency=2 , Burst Length=4 = VIH or VIL CKE CS RAS CAS WE A12/A13(BS) Address
DQM , DQMU/DQML R:a C:a R:b C:b
DQ(output) DQ(input)
Bank0 Active Active Clock Suspend Start a a+1 a+2
High-Z a+3 b b+1 b+2 b+3 Earliest Bank3 Precharge
Bank0 Bank3 Write Suspend Write Active Start
Bank3 Bank0 Write Precharge
Active Clock Suspend End
Write Suspend End
Write Cycle , RAS-CAS Delay=2 CAS Latency=2 , Burst Length=4 = VIH or VIL
53
LG Semicon Power Down Mode
GM72V66841CT/CLT
CLK CKE CS RAS CAS WE A12/A13(BS) Address
DQM , DQMU/DQML
A10=1
CKE Low
R:a
DQ(input) DQ(output)
High-Z
tRP
Precharge Command if needed Power Down Entry Power Down Mode Exit Active Bank 0
Power Down Cycle
RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL
54
LG Semicon Power Up Sequence
0 1 2 3 4 5 6 7 8 9 10 48 49
GM72V66841CT/CLT
50
51
52
53
54
55
CLK CKE CS RAS CAS WE Address
DQM , DQMU/DQML
VIH
Valid
code
Valid
VIH
High-Z
DQ
tRP
All banks Precharge Auto Refresh
tRC
Auto Refresh
tRC
tRSA
Mode Register Set Bank Active if needed
55
LG Semicon
GM72V66841CT/CLT
Package Dimensions
GM72V66841CT/CLT Series (TTP-54D)
Preliminary
22.22 54 22.72 Max 28
Unit: (mm)
1 0.30 0.28+/- 0.05
+0.10 - 0.05
0.80
27
0.13 M
0.80
10.16
0.91 MAX
11.76+/- 0.20
0~5
0.145+/- 0.05
0.125+/- 0.04
0.13+/- 0.05
1.20 MAX
0.10
0.50+/- 0.10
Hitachi Code JEDEC Code
Dimension including the plating thickness Base material dimension
TTP-54D 0.53g
EIAJ Code Weight(reference value)
56
0.68

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